1. Field of the Invention
The invention in general relates to apparatus and methods of testing electrical circuits and more particularly to apparatus and methods of testing circuits which include some circuit elements that include boundary-scan logic and some circuit elements that do not include boundary-scan logic.
2. Statement of the Problem
The testing of electrical circuits is nearly as old as electrical circuits themselves. In simple circuits this is done by applying small voltages to all the circuit nodes to test for shorts or open circuits. The term node in this specification means any equipotential circuit element; an example is a connecting wire or trace between two electrical components. As circuits have become more complex it has become ever more important and more difficult to thoroughly test circuits. A common way of doing this is to design a testing apparatus and method as part of the development program for every manufactured circuit, such as a circuit board for a TV. Generally a program is developed which is programmed into a complex testing machine which includes hundreds or even thousands of resources, such as voltage drivers and receivers, which are alternately connected to the nodes of the circuit via relays and contact nails in a programmed sequence to test the circuit. In complex circuits not every combination of nodes can be tested, since this could take longer than the age of the universe. So the test designer must develop some way to make sure that the nodes most likely to fail in the particular circuit are tested. This has become a very complex science utilizing higher mathematics and computers. See for example U.S. Pat. No. 4,601,032 issued to Gordon D. Robinson which devises and applies a complex waveform of test vectors (a set of digital voltages applied to a set of nodes) to the circuit elements to test the circuit, and U.S. Pat. No. 5,027,353 issued to Najmi T. Jarwala et al., which uses a weighted mathematical system to determine a compact set of test vectors to test the circuit. One problem with such tests is that the vectors or waves, which are pulses of voltage applied to the system, can damage the system, especially if there is a fault in the system and the voltages are applied for too long of a period. This can often happen because the systems are so complex that it takes a long time to run such tests. Another problem is that generally the better such tests are at finding that there is a circuit fault, the less likely it is that they are able to locate precisely where the circuit fault is. Since complex circuit boards are expensive, it is essential to know where the fault is so that it can be repaired. Another problem is that in modern electronic circuits with surface mount, fine geometries, and double-sided boards, not all nodes will be accessible, and thus cannot be tested by such methods.
One solution to the problem of potentially damaging devices during powered tests is found in U.S. Pat. No. 4,588,945 issued to William A. Groves et al., which describes a method of testing which provides a time limit for applying test signals and a cool down time in between test signals, the length of which time limit and cool down time is determined from the characteristics of the devices tested.
One solution to the problem of precisely locating system faults when not all nodes are accessible is called boundary-scan. Boundary-scan is a test system in which each component of a circuit, such as a chip, is constructed with a set of shift registers placed between each device pin and with a specific internal logic system. This system has been defined in an IEEE standard No. 1149.1-1990. The boundary-scan standard allows the entire circuit to be accurately tested by scanning only the boundary pins of the circuit. For a complete description of boundary-scan see HP Boundary-Scan Tutorial and BSDL Reference Guide, published by Hewlett Packard Company, Manual Part No. E1017-90001. See also U.S. Pat. No. 4,872,169 issued to Lee D. Whetsel, Jr., U.S. Pat. No. 4,879,717 issued to Wilhelm A. Sauerwald et al., U.S. Pat. No. 4,967,142 issued to Wilhelm A. Sauerwald et al., European patent application number 89308562.1 of Lee D. Whetsel, Jr., and European patent application No. 90305582.0 of Najmi T. Jarwala et al. which disclose various details of the implementation of boundary-scan.
The boundary-scan system described in the above references produces excellent results in circuits which are composed wholly of boundary-scan circuit elements. However, in the real world there are very few such systems. Usually an electronic circuit is composed of elements made by a wide variety of manufacturers, many of which do not use the boundary scan standard. The above references do not teach how to address the problem of testing such circuits.
The testing of mixed circuits, i.e. circuits which contain both conventional and boundary-scan circuit elements by boundary scan techniques presents two significant problems: 1) the boundary-scan test is a powered test--this means that in the presence of potentially damaging shorts, the circuit is powered and can be damaged; and 2) the presence of non-boundary scan elements compromises the boundary scan test in that a short between a non-boundary-scan element and a boundary-scan element will often cause the boundary scan node to have the wrong logic value, and the results are not likely to be repeatable because the conventional logic is on and is not predictable. See Interconnect Testing of Boards with Partial Boundary Scan, Gordon D. Robinson & John G. Deshayes, IEEE 1990 International Test Conference Proceedings, CH29100-6/000/0572, Paper 27.3, pages 572-581. The above paper discloses a method of solving the problem by a four part test: first, a conventional shorts test is done between all places to which the tester has access; second, the boundary circuit test circuitry and the path segments between components are tested to see they are working properly; third, a test for shorts between nodes with tester access and the boundary scan nodes without access are tested; Finally, a test for opens and shorts on the pure boundary scan nodes. The third test can have two forms. The simplest tests one node at a time; it forces a high on the node, does a boundary scan test, then forces a low on the node and performs another boundary scan test. If there is a short, one of these tests will likely produce a wrong result on the boundary scan test. The other form of the third test tests several nodes at once and each node is given a unique identifier signal. A short is declared when one of the boundary scan test nodes sees one of the identifiers. The problem with this test is that using the simplest form of the third test can take unacceptably long and use a large number of resources in a complex circuit and using the second form of the third test gives ambiguous results since the identifier can propagate to the boundary-scan node through nodes other than the driven node. This test also takes a long time since the number of sets to be tested can be very large.
Another system for testing mixed conventional and boundary-scan nodes is disclosed in U.S. Pat. No. 4,963,824 issued to Edward P. Heleb et al. The method disclosed replaces each circuit board component in turn with a testing device. The method also discloses isolating non-boundary scan components by applying special connector cards with boundary scan capabilities to the connectors around the component. This method is impractical since removing the devices and replacing them not only is unwieldy and time consuming, but destroys the very basis of the test: since the component must be replaced, and since the replacement can cause shorts or opens, the board should be retested afterwards. Attaching special cards to isolate the non-boundary scan components not only is time consuming, but assumes that the cards can be connected which is often not the case in complex, surface mounted and double sided boards.
In sum a need still exists for a test apparatus and method for mixed conventional and boundary-scan circuits that tests more than one node at a time, reduces the set of nodes tested to a manageable number, can unambiguously detect circuit faults, and does not require the physical alteration of the circuit.
3. Solution to the problem
The invention provides apparatus and methods for performing boundary-scan tests on mixed circuits that reduces the number of nodes to be simultaneously tested to a manageable number.
The invention provides apparatus and methods for performing boundary-scan testing of mixed circuits that permits the precise node that has the fault to be determined.
The invention provides apparatus and methods for performing boundary-scan tests on mixed circuits that for a given boundary-scan node tests only a relatively small set R of non-boundary scan nodes, where the set R is the set of all accessible non-boundary-scan nodes within a radius R of the boundary scan node, where R is a length related to the length of solder bridges on the circuit board to be tested.
The invention provides apparatus and methods for boundary-scan testing of mixed circuits that, if a set R is found which includes a fault, resolves the precise node of the set R that is causing the fault.
The invention also provides apparatus and methods for performing boundary-scan tests on mixed circuits that prevents damage to the circuit due to power being applied for too long a time.
The invention provides apparatus and methods for boundary-scan testing of mixed circuits that provides a test time limit for each boundary-scan node to be tested in the circuit, orders the boundary-scan nodes to be tested so that those with the shortest test time limit are tested first, and shuts off the power when the time limit is reached for nodes that have not been tested.